1. Field of the Invention
The present invention relates to a semiconductor device including a memory region and a logic region embedded on a semiconductor substrate.
2. Description of the Related Art
With a semiconductor device including a memory element, a pattern collapse that happens when forming a repetition pattern of a memory cell has been one of serious issues to be overcome.
Accordingly, JP-A No. 2001-68636 proposes a technique to prevent the pattern collapse. This document discloses a technique of disposing one or more dummy cells of a same shape as a memory cell, but without a memory function, at an end of a memory cell array of a semiconductor device so as to restrain a pattern collapse of the working memory cell, to thereby reducing a yield loss.
Also, JP-A No. 2003-100910 discloses a technique of providing a dummy cell plug in a semiconductor device including a memory region constituted of DRAM memory cells and a logic region, though this is intended for a different purpose. In the structure disclosed therein, the memory region includes an effective memory cell region and a dummy cell region provided around a periphery of the effective memory cell region. The dummy cell region is provided with an upper electrode extension led from the upper electrode of the DRAM memory cell, and the dummy cell plug is located below the upper electrode extension.